The invention relates generally to semiconductor device and integrated circuit fabrication and, in particular, to device structures and fabrication methods for an on-chip resistor.
On-chip resistors are passive devices found in many integrated circuits. An on-chip resistor may be formed by depositing a layer of resistor material having a given thickness and patterning the resistor material layer to provide a resistor body that is dimensioned to a particular length and width. The resistance of an on-chip resistor is based on a combination of physical properties (e.g., cross-sectional area and length) and material properties (i.e., resistivity).
The resistor body may be formed in a space that is arranged vertically between the first metallization level of a back-end-of-line (BEOL) structure and the front-end-of-line (FEOL) device structures. The space also includes a dielectric layer on which the resistor body is formed and contacts that connect the metal features in the first metallization level with the front-end-of-line device structures and with the resistor body. With downward scaling, the thicknesses of the dielectric layer and the resistor body may become roughly equal, which is problematic when forming contacts extending vertically from one of the metal features to the resistor body.